In a basic typical arrangement, memory cells may, be arranged in a matrix fashion, wherein, in one direction, the memory cells may be connected to common word lines, and in an orthogonal direction they may be connected to common bit lines. More hierarchies may be based on this arrangement, but this may be irrelevant here.
An “erase” operation may affect all the memory cells connected to at least one word line, setting all of them to a value defining an unwritten state, e.g., to ‘1’.
A “write” operation may affect some memory cells connected to one word line, setting them to a value defining a written state, e.g., to ‘0’, wherein the specific memory cells to be written may be selected through the bit lines.
A “read” operation may read out some memory cells connected to one word line, resulting in data consisting of ‘1’s and ‘0’s, wherein the specific memory cells to be read may be selected through the bit lines.
For all of these operations, an address may define which word line and (except for the erase operation) which bit lines are to be operated on.
For an operation of a highly secure memory, it may be essential to be able to reliably verify that the memory operations like erase, write, and read are or have been really performed on the intended memory cells, even in a case of an attacker having physical access to the chip.
This may be difficult to achieve, if one has to assume that the attacker is not only able to manipulate the erase, write, and/or read operations, but also to manipulate the verify operation itself.
In part, this aim may currently be achieved by using an address dependent data encryption. However, by this, not all relevant cases may be covered.